Semiconductor memory devices, such as erasable, programmable, read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), and flash erasable programmable read-only memories (FEPROMs) are erasable and reusable, and are employed in various commercial electronic devices, such as computers, cellular telephones and digital cameras. There has recently evolved devices termed mirrorbit devices which do not contain a floating gate electrode. In mirrorbit devices, the gate electrode is spaced apart from the substrate by an oxide/nitride/oxide (ONO) stack, such as a silicon oxide/silicon nitride/silicon oxide stack. In such devices, the charge is contained within the nitride layer of the ONO stack. The relentless drive for miniaturization has led to the fabrication of various types of flash memory devices comprising transistors having a gate width of about 150 nm and under, and gate structures spaced apart by a gap of 225 nm or less. Conventional practices comprise forming a sidewall spacer on side surfaces of the gate stack, thereby reducing the gate gap to about 25 nm.
As device dimensions shrink into the deep sub-micron regime, vulnerability to mobile ion contamination, such as hydrogen ion degradation, increases, and it becomes increasingly more difficult to satisfactorily fill high aspect ratio gaps between neighboring transistors, as well as to satisfactorily fill high aspect ratio openings, such as shallow trenches for trench isolation structures and gaps between metal lines, such as bit lines and aluminum lines. The inability to adequately getter mobile ion contaminants, such as hydrogen ions, results in a neutralization of electrons and, hence, leakage causing programming loss as well as a charge gain causing reappearance of erased information. The inability to adequately fill gaps between neighboring transistors leads to void formation and an open contact with consequential shorting between contacts causing leakage and low production yields.
A pre-metal dielectric layer or first interlayer dielectric (ILD0) is typically deposited over gate electrode structures filling the gaps, followed by rapid thermal annealing. Conventional practices comprise depositing a boron-phosphorous-silicon oxide derived from tetraethyl orthosilicate (BPTEOS) or a phosphorous doped high density plasma (P-HDP) oxide as the ILD0. However, such oxides fall short of addressing both the mobile ion contamination and void formation problems.
The inability to satisfactorily fill other various openings and gaps during semiconductor fabrication leads to various problems, including void formation and short circuiting. There have recently become available various low deposition temperature dielectric materials designed to fill high aspect ratio openings and gaps, such as openings and gaps having an aspect ratio of 3:1 or greater. Such materials include, for example, Aziva Flowfill materials manufactured by Aziva Technology, Inc. located in Newport, England; and HARP (Applied Materials High Aspect Ratio Fill Process) available from Applied Materials located in Santa Clara, Calif. Other conventional spin-on materials designed to fill high aspect ratio openings include BPTEOS, boron-doped silicon oxide derived from tetraethyl orthosilicate (BTEOS); and phosphorous-doped silicon oxide derived from tetraethyl orthosilicate (PTEOS). Such materials are conventionally deposited and then subject to post deposition annealing in order to increase the density of the deposited material, improve wet etch characteristics and improve moisture resistance. However, the effective deposition of such materials in high aspect ratio openings remains problematic, because the deposited material within the opening, typically at the bottom of the opening, does not exhibit the same properties as the deposited material at the top of the opening or at a distance from the opening. As a result of such a difference in properties or inhomogeneities, the dielectric material proximate the bottom of the filled opening exhibits a wet etch rate significantly greater than the wet etch rate of the dielectric material in other areas, such as at the upper portion of the filled opening or at a distance from the opening. Further, it was found that after curing voids existed in the bottom of the opening. Such nonuniformities and voids lead to various problems, including short circuiting and leakage, as well as low production yields.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices with improved reliability, increased operating speed, reduced device leakage and homogenously deposited dielectric layers filling gaps and openings. There exists a particular need for methodology enabling the fabrication of flash memory devices, such as mirrorbit devices, with improved data retention, increased opening speed, reduced device leakage, homogeneously filled gaps and openings, and improved reliability.